SiFive Launches First RISC-V Based CPU Core with Linux Support

SAN MATEO, Calif. – Oct. 4, 2017 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced the availability of U54-MC Coreplex IP, the industry’s first RISC-V based, 64-bit, quadcore real-time capable application processor with support for full featured operating systems such as Linux. The free and open RISC-V architecture, which is supported by an ecosystem comprising more than 70 companies, has seen tremendous growth in the embedded segment. The release of the U54-MC Coreplex marks the architecture’s expansion into the application processor space – opening entirely new use cases for RISC-V.

RISC-V is a free and open instruction set architecture (ISA) designed to enable chips across the full spectrum of computing devices, from embedded devices to the data center. As the first RISC-V application processor capable of running embedded Linux, the standard U54-MC Coreplex contains four U54 CPUs along with a single E51 CPU, and is the first commercial RISC-V core to include multicore support and cache coherence. Each U54 CPU utilizes a highly efficient five-stage in-order pipeline. The U54 cores support the RV64GC ISA, which is expected to be the standard for Linux-based RISC-V devices. The 64-bit E51 CPU serves as a management core and is fully coherent with the main U54 cores. The U54-MC Coreplex is ideal for applications which need full operating system support such as AI, machine learning, networking, gateways and smart IoT devices.

"SiFive has achieved another significant milestone for the RISC-V community," said Rick O’Connor, executive director of the non-profit RISC-V Foundation. "The ability for RISC-V developers to develop Linux and other Unix-based operating systems on commercial grade silicon will enable the RISC-V software ecosystem to quickly expand beyond embedded systems, and bring new solutions to market. We look forward to seeing the various markets that are now addressable with SiFive’s U54-MC Coreplex IP."

SiFive’s U54-MC Coreplex has been taped out as part of SiFive’s Freedom Unleashed family of high-performance, customizable RISC-V SoCs. As implemented in the Freedom Unleashed platform, the U54 and E51 CPUs run at 1.5+ GHz in 28nm technology. Each of the U54 CPUs implement a 32KB Instruction Cache and 32KB Data Cache, and all of the cores share a coherent, 2MB L2 Cache. Customers can license the U54-MC Coreplex in a variety of configurations besides the 4+1 default configuration.

"The U54-MC Coreplex is the first fully Linux-compatible CPU based on RISC-V. It takes the industry one step closer to making custom silicon available to everyone," said Andrew Waterman, co-founder of SiFive. "We continue to be amazed by the support SiFive has received since we launched the industry’s first open-source RISC-V SoC last year, and look forward to additional milestones in the coming months."

Availability

A development board based on U54-MC Coreplex IP will be available in Q1 2018. For more information on the U-series Coreplex IP, please visit SiFive's Core Designer.

About SiFive

SiFive is the first fabless provider of customized semiconductors based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Yunsup Lee, Andrew Waterman and Krste Asanovic, SiFive democratizes access to custom silicon by helping system designers reduce time-to-market and realize cost savings with customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital and Osage University Partners. For more information, visit www.sifive.com.