SiFive Essential
7-Series

32-bit or 64-bit RISC-V core 

Up to 3.3 DMIPS/MHz, 5.8 CoreMark/MHz 

Superscalar dual issue, in-order 8 stage Harvard pipeline 

Coherent multicore capable with shared level 2 cache 

Optional SECDED ECC support on Level 1 and Level 2 memories 

Up to 47-bit physical addressing 

MMU (U7 only) 

Linux capable (U7 only)

Double, Single and Half-precision floating point 

Advanced Security options including WorldGuard 

Configurable range of Memory and SoC interface options 

• Flexible and configurable Port interfaces including IO coherent interface (Front Port) 
• Direct, dedicated Core Local Port for hardware peripheral / accelerator connectivity
• Industry standard AMBA compliant bus protocols enable easy integration