A Look Back: 7th RISC-V Workshop

A new year brings new opportunities. Before we dive into 2018, we wanted to take some time to reflect on some of the excitement we experienced over the last couple of months.

At the 7th RISC-V Workshop, we had the honor of partnering with some of the industry’s leading companies and announced the following at the workshop:

• An extended partnership with Microsemi: Microsemi and SiFive formed a strategic partnership to create and market a development board based on SiFive’s RISC-V based Freedom Unleashed 500 platform and Microsemi’s PolarFire FPGAs.

• Membership in GLOBALFOUNDRIES’ FDXcelerator Partner Program: SiFive has joined the GF program that brings together select partners to integrate their products or services into validated, plug-and-play design solutions. This provides GF customers access to SiFive RISC-V Core IP alongside a broad set of quality offerings specific to GF’s 22FDX technology.

In addition, many of our SiFive colleagues, including two of the creators of the RISC-V architecture, presented at the event. Our leading position in the ecosystem was highlighted in several partner presentations and posters including Lauterbach, Emdalo, OhChip, the University of Washington, and Berkeley Architecture Research. During the evening reception, traffic was brisk at the SiFive demo table, where we showed off our U54-MC Core IP running Quake on Linux, FreeRTOS running on our HiFive1 development board, and development tools including Segger Embedded Studio, Lauterbach Trace 32, and our own Freedom Studio.

Did we miss you at the event? No worries! You can catch up on the proceedings by watching the videos and downloading the slides below:

• Krste Asanovic on RISC-V State of the Union: Video and Slides
• Andrew Waterman on RISC-V Hypervisor Extensions: Video
• Jack Kang on the Freedom Unleashed 500, a Linux-capable, 1.5GHz quad-core SoC based on our U54-MC Core IP: Video
• Wesley Terpstra on TileLink, a free and open-source, high-performance scalable cache-coherent fabric designed for RISC-V: Video and Slides