Building the Future of AI on Intelligent Accelerators

Using SiFive’s X100-series as an Accelerator Control Unit (ACU)

In Pete Lewin’s previous blog post, The Perfect Solution for Local AI , he introduced some of the high-level thinking behind the creation of the SiFive Intelligence X100 product series and showed a performance comparison against an established incumbent. He, and I, discussed the rapid pace of innovation in the AI market and how that is making it incredibly challenging to design the “perfect” hardware accelerator. Instead, what we are seeing from customers is a desire to complement the accelerator with a programmable front end; what we term an accelerator control unit (ACU). This allows them to focus more of their efforts (and R&D spending) on the data-processing capabilities of the accelerator rather than control and management functions, which SiFive’s RISC-V-based approach does so well.

In this blog, I dive a little deeper into the options to efficiently couple a processor from the X100 series to a hardware accelerator. The diagram below highlights how customers are using X-series products as Accelerator Control Units (ACUs).

The integrated vector engine present in the X160 and X180 processors provides complementary compute capabilities that can also assist the accelerator in a range of tasks, including pre-/post-formatting of data and handling of corner cases. Basing this system capability on a product that is 100% compatible with the RISC-V instruction set architecture enables customers to select from a broad, and rapidly expanding set of application software, operating systems and development tool options.

Harnessing the X100 provides a standardized software development model for two different types of proprietary SiFive direct-to-core accelerator attachments which lower latency and improve overall performance.

• SiFive Scalar Coprocessor Interface (SSCI): New with Intelligence Gen 2, this interface allows the accelerator to be driven via RISC-V custom instructions with direct access to the registers within the X100 processor. Our customers are using this to control and configure a tightly coupled coprocessor.

• Vector Coprocessor Interface (VCIX): A high-bandwidth interface to support data movement to a matrix coprocessor. Using VCIX provides high-bandwidth access to CPU vector registers, lowers latency, and uses vector-type instruction formats to feed customers matrix engines with large datasets. This isn’t just for edge/IoT, VCIX is also being used in this way by large data center customers.

There is also the Core Local Port (CLP) that allows fast access to accelerator SRAM for companion compute on the CPU.

How does this work in practice? If we assume a SSCI-type of connector, the custom function might be something such as performing trigonometric functions, algorithm-specific bit manipulation or math functions, such as square root.

The custom logic only has to decode a few bits of the opcode and perform the actual operation being implemented. The existing CPU logic in the X100 handles the full decode of the instruction, selecting the source register, reading/writing from/to a destination register, performing data forwarding and managing pipeline stall / flush functions.

Are you wrestling with creating the optimal system architecture for a next-generation platform? Tasked with bringing AI to your IoT workloads? The SiFive Intelligence Family was designed for AI and is a popular solution for a growing number of applications and could be your perfect solution. SiFive can help with modeling tools and free system architecture reviews to de-risk and accelerate your program.

Check out this case study to see how customers are already putting these new products to work:
Tier 1 US Semiconductor Company Licenses SiFive X160 for Industrial MCU Applications.

Author

Ian Ferguson is the Vice President of Vertical Markets and Business Development at SiFive, where he is responsible for accelerating growth of the company across a range of growth segments including data centers, consumer and automotive market segments. Of particular focus is how artificial intelligence offers an opportunity for industries to shift from incumbent architectures to the RISC-V open standard. Prior to joining SiFive Ian worked at Lynx Software Technologies as the vice president of marketing at Lynx Software Technologies, responsible for all aspects of the outward-facing presence of the company to its customer, partner, press and analyst communities. Ian was a key part of the team that was responsible for selling the company to OceanSound Partners, a private equity firm. Ian also spent nearly 11 years at Arm, where he held various roles leading teams in vertical marketing, corporate marketing and strategic alliances. Ian is a graduate of Loughborough University (UK) with a bachelor’s degree in electrical and electrical engineering.