资源与支持

SiFive 博客

来自 RISC-V 专家的最新洞察与深度技术解析

October 19, 2018

Last Week in RISC-V: October 19, 2018

It's been another week, which means it's time to find another host for "Last Week in RISC-V". This week we're going to attempt a blog at riscv.org, which will hopefully be a good long-term home for this series of articles.

As usual, you can find this week's entry on GitHub.

glibc Floating-Point Test Suite

As part of the RV32I glibc submission process, Zong from Andes has submitted a glibc patch set to fix a generic floating-point bug that crosses the boundary between GCC and glibc. There's been a bit of feedback that, quite honestly, I don't understand -- the combination of floating-point and glibc macros pretty much guarantees that I won't be able to read the diff.

Luckily, it appears some smart glibc maintainers have figured out what's going on and have helped Zong work through some issues. I look forward to the v2 patch set!

binutils-2.31.1 Backports

Kito from Andes has backported a handful of fixes RISC-V specific fixes to binutils-2.31.1. The most important fix here is to avoid generating incorrect executables with PC-relative relocations that have addends, as was discussed in a previous post. Like usual, anyone distributing RISC-V toolchains should update.

Floating-Point Support in ptrace()

Jim has submitted a patch to add floating-point support to our ptrace() implementation. There are some interface issues in this version, but I'm sure they'll get ironed out in time for the 4.20 merge window.

MUSL Support in riscv-gnu-toolchain

Nick Kossifidis has opened a PR to add support for MUSL to `riscv-gnu-toolchain', which should be useful for anyone working on our MUSL port. We're not upstream there yet, but reading the patches that Michael Clark sent upstream is still on my TODO list!

HiFive Unleashed Linux Drivers

Paul has posted a driver for the sifive,uart0 serial controller as well as the associated device tree binding to the Linux mailing lists. There are some issues, but hopefully they'll get resolved soon.

Additionally, Atish has a patch set containing drivers for our GPIO and PWM controller that was posted to the list last week.

Events

Read more Insights from the RISC-V Experts

X100 系统安全防护:RISC-V 边缘端的 AI
Blog Post
X100 系统安全防护:RISC-V 边缘端的 AI
边缘 AI 是多种技术的融合,包括人工智能、物联网、边缘计算和嵌入式系统。它们共同发挥关键作用,使智能处理和决策能够在网络边缘实现。边缘 AI 利用嵌入式算法监控远程系统的活动,并处理由传感器及其他数据采集装置收集的非结构化数据,如温度、语言、脸部、运动、图像、距离及其他模拟输入信号。
在智能加速器上构建 AI 的未来 
Blog Post
在智能加速器上构建 AI 的未来 
在之前的《本地 AI 的完美解决方案》文章中,我们介绍了 SiFive Intelligence X100 产品系列的部分高层设计理念,并展示了与其他成熟厂商的性能对比。我们还讨论了 AI 市场的快速创新,以及这如何使设计“完美”的硬件加速器变得极具挑战性。而从客户那里可以看到的是,他们希望在加速器之外配备一个可编程的前端,我们称之为加速器控制单元(ACU)。这使得客户能将更多精力(和研发支出)集中在加速器的数据处理能力上,而控制和管理功能则交由 SiFive 基于 RISC-V 的方法来实现。
赋能远端边缘的 AI 创新
Blog Post
赋能远端边缘的 AI 创新
当前行业的焦点,更多投向那些能够将数据中心 AI 性能推向更高峰的硬件技术上。在 HotChips 2025 大会期间,对超大规模计算性能提升的需求占据绝大多数议程,而功能强大的大型芯片则成为了焦点。
Got a question?

Our AI chatbot can help!

Chat Now