RISC-V Chiplets, Disaggregated Die, and Tiles
Scalable High-Performance Computing SoC Design with RISC-V
Whether you refer to the design concept as a disaggregated die, tiles, chiplets, or good ol’ multi-chip modules, a growing trend among SoC designers is making the interposer act like a ‘mainboard’ to host multiple chips. Together, these chip...