Part 4: High-Performance Interconnect for Accelerators: Enabling Optimized Data Transfers with RISC-V
This is the fourth in a series of blogs about Domain-specific accelerators (DSAs), which are becoming increasingly common in systems-on-chip (SoCs). Parts 1, 2 and 3 addressed key challenges such as data transfers between DSAs and the core complex, point-to-point ordering between cores and DSA memor...