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Building a secure foundation using the concept of randomness seems, on the surface, counter-intuitive. As an aspect of entropy, randomness enables the generation of cryptographic methods to protect data, chips, and systems. By harnessing the nature of randomness as the basis of a secure system, it i...

The RISC-V Vector extension (RVV) enables processor cores based on the RISC-V instruction set architecture to process data arrays, alongside traditional scalar operations to accelerate the computation of single instruction streams on large data sets. The RISC-V International vector working group is ...

OpenFive is a solution-centric and processor agnostic custom silicon business unit dedicated to building optimized domain-specific SoCs Today, I am excited to announce the launch of OpenFive, a self-contained and autonomous custom silicon business unit of SiFive, Inc. OpenFive is solution-centric an...

SiFive's Best Processor Portfolio Is Here We’re pleased to announce a comprehensive update to SiFive’s RISC-V IP Portfolio with the SiFive 20G1 release. This release brings important enhancements and new capabilities to SiFive Core IP, the industry's broadest RISC-V IP Portfolio, ranging from the ul...

A Message From The CEO Innovation in SiFive’s product portfolio and business model differentiates our company, but the employee team is the heart of our success. SiFive employees enable our company to offer the full idea-to-silicon journey, from configurable processor cores with comprehensive pre-in...

Published by SemiWiki. Before the advent of RISC-V, designers looking for embedded processors were effectively limited to a handful of proprietary processors using ISAs from decades ago. While the major ISAs are being updated and enhanced, they also are facing limitations from many decisions made ov...